// Copyright (C) 1953-2022 NUDT
// Verilog module name - teststart_enable_generate 
// Version: V4.3.0.20230901
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
///////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module teststart_enable_generate(
input                 i_clk_125m,
input                 i_rst_n,
input                 i_cyclestart_s1,
input                 i_cyclestart_s2,
input                 i_cyclestart_A,
input                 i_cyclestart_B, 
input                 i_cyclestart_C,
input                 i_cyclestart_D,     
output reg            o_teststart_en
);         
reg       [5:0]       rv_pps_flag;
reg       [5:0]       rv_cycle_cnt;

reg       [1:0]     tsg_state;
localparam          IDLE_S       	 = 2'd0,
					PULSE_OK_S   	 = 2'd1,
                    DELAY_S          = 2'd2;

always@(posedge i_clk_125m or negedge i_rst_n)begin 
    if(!i_rst_n) begin
		o_teststart_en   <=1'd0;
		rv_pps_flag      <=6'd0;
		rv_cycle_cnt     <=6'd0;
        tsg_state        <=IDLE_S;
    end
    else begin
        case(tsg_state)	
        IDLE_S:begin  	
			if(i_cyclestart_s1==1'b1)begin  
				rv_pps_flag[0]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[0]<=rv_pps_flag[0];
            end
			if(i_cyclestart_s2==1'b1)begin  
				rv_pps_flag[1]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[1]<=rv_pps_flag[1];
            end
			if(i_cyclestart_A==1'b1)begin  
				rv_pps_flag[2]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[2]<=rv_pps_flag[2];
            end
			if(i_cyclestart_B==1'b1)begin  
				rv_pps_flag[3]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[3]<=rv_pps_flag[3];
            end
			if(i_cyclestart_C==1'b1)begin  
				rv_pps_flag[4]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[4]<=rv_pps_flag[4];
            end
			if(i_cyclestart_D==1'b1)begin  
				rv_pps_flag[5]<=1'b1;
            end			
            else begin				             
				rv_pps_flag[5]<=rv_pps_flag[5];
            end
			o_teststart_en   <= o_teststart_en;
			if(|rv_pps_flag[5:0]==1'b0)begin			
				rv_cycle_cnt  <=6'd0;
				tsg_state     <=IDLE_S;
            end			
            else begin	
				rv_cycle_cnt  <=rv_cycle_cnt+1'b1;
				tsg_state     <=PULSE_OK_S;
            end
        end
        PULSE_OK_S:begin 
			if(rv_cycle_cnt<6'd51)begin
				if(rv_pps_flag[0]==1'b1)begin  
					rv_pps_flag[0]<=rv_pps_flag[0];
				end			
				else begin				             
					if(i_cyclestart_s1==1'b1)begin
						rv_pps_flag[0]<=1'b1;
					end
					else begin 
						rv_pps_flag[0]<=rv_pps_flag[0];
					end
				end
				if(rv_pps_flag[1]==1'b1)begin  
					rv_pps_flag[1]<=rv_pps_flag[1];
				end			
				else begin				             
					if(i_cyclestart_s2==1'b1)begin
						rv_pps_flag[1]<=1'b1;
					end
					else begin 
						rv_pps_flag[1]<=rv_pps_flag[1];
					end
				end
				if(rv_pps_flag[2]==1'b1)begin  
					rv_pps_flag[2]<=rv_pps_flag[2];
				end			
				else begin				             
					if(i_cyclestart_A==1'b1)begin
						rv_pps_flag[2]<=1'b1;
					end
					else begin 
						rv_pps_flag[2]<=rv_pps_flag[2];
					end
				end				
				if(rv_pps_flag[3]==1'b1)begin  
					rv_pps_flag[3]<=rv_pps_flag[3];
				end			
				else begin				             
					if(i_cyclestart_B==1'b1)begin
						rv_pps_flag[3]<=1'b1;
					end
					else begin 
						rv_pps_flag[3]<=rv_pps_flag[3];
					end
				end				
				if(rv_pps_flag[4]==1'b1)begin  
					rv_pps_flag[4]<=rv_pps_flag[4];
				end			
				else begin				             
					if(i_cyclestart_C==1'b1)begin
						rv_pps_flag[4]<=1'b1;
					end
					else begin 
						rv_pps_flag[4]<=rv_pps_flag[4];
					end
				end				
				if(rv_pps_flag[5]==1'b1)begin  
					rv_pps_flag[5]<=rv_pps_flag[5];
				end			
				else begin				             
					if(i_cyclestart_D==1'b1)begin
						rv_pps_flag[5]<=1'b1;
					end
					else begin 
						rv_pps_flag[5]<=rv_pps_flag[5];
					end
				end
				if(&rv_pps_flag[5:0]==1'b1)begin  
					rv_cycle_cnt  <=6'd0;
					rv_pps_flag   <=6'd0;
					o_teststart_en<=1'b1;
					tsg_state     <=DELAY_S;
				end			
				else begin	
					rv_cycle_cnt  <=rv_cycle_cnt+1'b1;
					o_teststart_en<=o_teststart_en;
					tsg_state     <=PULSE_OK_S;
				end
			end
			else begin 
				if(&rv_pps_flag[5:0]==1'b1)begin  
					o_teststart_en<=o_teststart_en;
				end			
				else begin	
					o_teststart_en<=1'b0;
				end				
				rv_cycle_cnt  <=6'd0;
				rv_pps_flag   <=6'd0;
				tsg_state     <=DELAY_S;			 		
			end
        end	 
        DELAY_S:begin
			if(rv_cycle_cnt<6'd3)begin  
				rv_cycle_cnt  <=rv_cycle_cnt+1'b1;
				tsg_state     <=DELAY_S;
			end			
			else begin	
				rv_cycle_cnt  <=6'd0;
				tsg_state     <=IDLE_S;
			end						
		end  		
        default:begin
			rv_cycle_cnt  <=6'd0;
			rv_pps_flag   <=6'd0;
			o_teststart_en<=1'b0;
			tsg_state     <=IDLE_S;	
		end  
        endcase           
    end       
end
endmodule